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F. A. Aloul, A. Ramani, I. L. Markov, K. A. Sakallah Many important tasks in circuit design and verification can be per-
 

Summary: F. A. Aloul, A. Ramani, I. L. Markov, K. A. Sakallah
Abstract
Many important tasks in circuit design and verification can be per-
formed in practice via reductions to Boolean Satisfiability (SAT), mak-
ing SAT a fundamental EDA problem. However such reductions often
leave out application-specific structure, thus handicapping EDA tools
in their competition with creative engineers. Successful attempts to rep-
resent and utilize additional structure on Boolean variables include re-
cent work on 0-1 Integer Linear Programming (ILP) and on symmetries
in SAT. Those extensions gracefully accommodate well-known ad-
vances in SAT-solving, but their combined use has not been attempted
previously. Our work shows (i) how one can detect and use symmetries
in instances of 0-1 ILP, and (ii) what benefits this may bring.
1. Introduction
Recent impressive speed-ups of solvers for Boolean satisfiability
(SAT) [15] enabled new applications in design automation [1, 10, 16].
Reducing an application to SAT facilitates the reuse of existing effi-
cient computational cores and leads to high-performance EDA tools
with little development effort. However, major concerns about this ap-
proach are the loss and ignorance of high-level information and appli-

  

Source: Aloul, Fadi - Department of Computer Engineering, American University of Sharjah

 

Collections: Engineering