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Exposing and exploiting internal parallelism in MEMS-based storage
 

Summary: Exposing and exploiting internal parallelism
in MEMS-based storage
Steven W. Schlosser Jiri Schindler Anastassia Ailamaki
Gregory R. Ganger
March 2003
CMU-CS-03-125
School of Computer Science
Carnegie Mellon University
Pittsburgh, PA 15213
Abstract
MEMS-based storage has interesting access parallelism features. Specifically, subsets of a MEMStore's thousands of
tips can be used in parallel, and the particular subset can be dynamically chosen. This paper describes how such
access parallelism can be exposed to system software, with minimal changes to system interfaces, and utilized cleanly
for two classes of applications. First, background tasks can utilize unused parallelism to access media locations with
no impact on foreground activity. Second, two-dimensional data structures, such as dense matrices and relational
database tables, can be accessed in both row order and column order with maximum efficiency. With proper table
layout, unwanted portions of a table can be skipped while scanning at full speed. Using simulation, we explore
performance features of using this device parallelism for an example application from each class.
We thank the members and companies of the PDL Consortium (including EMC, Hewlett-Packard, Hitachi, IBM, Intel, Microsoft, Network
Appliance, Oracle, Panasas, Seagate, Sun, and Veritas) for their interest, insights, feedback, and support. We thank IBM and Intel for hardware

  

Source: Ailamaki, Anastassia - School of Computer Science, Carnegie Mellon University
Carnegie Mellon University, School of Computer Science
Ganger, Greg - Department of Electrical and Computer Engineering, Carnegie Mellon University

 

Collections: Computer Technologies and Information Sciences