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Automatatheoretic Verification of RealTime Systems Rajeev Alur

Summary: Automata­theoretic Verification of Real­Time Systems
Rajeev Alur
Computing Science Research
AT&T Bell Labs
Murray Hill, NJ 07974.
email: alur @ research.att.com
David Dill
Computer Science Department
Stanford University
Stanford, CA 94305
email: dill @ cs.stanford.edu
November 2, 1995
1 Introduction
Formal methods for specifying, analyzing, and manipulating the behavior of concurrent systems
become much more attractive in practical use if they can be automated. A number of methods
based on finite­state representations have achieved considerable success in practical applications
such as protocol and hardware verification, precisely because many problems are decidable for
finite­state representations. Finite­state verification methods include checking equivalences (such as
bisimulation), preorders (such as simulation), temporal logic properties (eg. CTL model­checking),
and inclusion of the language of one automaton in another.


Source: Alur, Rajeev - Department of Computer and Information Science, University of Pennsylvania


Collections: Computer Technologies and Information Sciences