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> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Abstract--The aggressive scaling of CMOS into the deep
 

Summary: > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1
Abstract-- The aggressive scaling of CMOS into the deep
submicron/nano ranges has resulted in an increased sensitivity to
externally induced phenomena such as soft errors. Tolerance to
soft errors, however, must be met while retaining high static
stability, low delay, and a low power supply in circuit operation.
This paper proposes a new design for hardening CMOS memory
cell at the nano feature size of 32nm. By separating the circuitry
for the write and read operations, the static stability of the
proposed cell configuration increase more than 4.4 times and 5
times at typical and slow process corners, respectively compared
to the previous designs. Simulation shows that by appropriately
sizing the pull-down transistors, the proposed cell results in a 40%
higher critical charge and 13% less delay than the conventional
design. Moreover, the proposed hardened cell is less susceptible to
process and random variations. Simulation results are provided
using the predictive technology file for 32nm feature size in
CMOS to show that the proposed hardened memory cell is best
suited when designing memories for both high performance and
soft error tolerance.

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering