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Synthesizable Reconfigurable Array Targeting Distributed Arithmetic for System-on-Chip Applications
 

Summary: Synthesizable Reconfigurable Array Targeting Distributed Arithmetic for
System-on-Chip Applications
Sami Khawam1
, Tughrul Arslan1,2
and Fred Westall3
1
School of Engineering and Electronic, The University of Edinburgh, King's Buildings,
Mayfield Road, Edinburgh EH9 3JL, UK. S.Khawam@ee.ed.ac.uk
2
Institute for System Level Integration, Livingston, EH54 7EG, UK
3
EPSON Scotland Design Centre, Integration House, Livingston, EH54 7EG, UK
Abstract
Domain-specific reconfigurable arrays are embedded
arrays optimized for one domain of applications
providing performance improvements over generic
embedded Field Programmable Gate Arrays (FPGAs). In
this paper, an embedded reconfigurable array that targets
Distributed Arithmetic (DA) implementations is
presented. DA includes calculations that are commonly

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering