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Summary: MLP-aware Instruction Queue
Resizing: The Key to Power-
Efficient Performance
Pavlos Petoumenos1
, Georgia Psychou1
, Stefanos Kaxiras1
,
Juan Manuel Cebrian Gonzalez2, and Juan Luis Aragon2
1
Department of Electrical and Computer Engineering, University of Patras, Greece
2
Computer Engineering Department, University of Murcia, Spain
Abstract. Several techniques aiming to improve power-efficiency (measured
as EDP) in out-of-order cores trade energy with performance. Prime exam-
ples are the techniques to resize the instruction queue (IQ). While most of
them produce good results, they fail to take into account that changing the
timing of memory accesses can have significant consequences on the memo-
ry-level parallelism (MLP) of the application and thus incur disproportional
performance degradation. We propose a novel mechanism that deals with this
realization by collecting fine-grain information about the maximum IQ resiz-
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