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[11] Pok, D., Chen, C., Schamus, J., Montgomery, C., and Chip design for monobit receiver.

Summary: [11] Pok, D., Chen, C., Schamus, J., Montgomery, C., and
Tsui, J.
Chip design for monobit receiver.
IEEE Transactions on Microwave Theory and Techniques,
45 (Dec. 1997).
[12] Grajal, J., Bl´azquez, R., L´opez-Risue~no, G., Sanz, J. M.,
Burgos, M., and Asensio, A.
Analysis and characterisation of a monobit receiver for
electronic warfare.
IEEE Transactions on Aerospace and Electronic Systems,
39, 1 (Jan. 2003).
[13] Sanchez, M., Garrido, M., L´opez-Vallejo, M., and
L´opez-Barrio, C.
Automated design space exploration of FPGA-based FFT
architectures based on area and power estimation.
In Proceedings of IEEE International Conference on Field
Programmable Technology (FPT 2006), 2006, 127--134.
[14] Yun-Nan, C., and Parhi, K.
An efficient pipelined FFT architecture.
IEEE Transactions on Circuits and Systems II, 50, 6


Source: Azimi-Sadjadi, Mahmood R. - Department of Electrical and Computer Engineering, Colorado State University


Collections: Computer Technologies and Information Sciences