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XI E. CHEN AND TOR M. AAMODT 1 Modeling Cache Contention and Throughput of
 

Summary: XI E. CHEN AND TOR M. AAMODT 1
Modeling Cache Contention and Throughput of
Multiprogrammed Manycore Processors
Xi E. Chen and Tor M. Aamodt, Member, IEEE
Abstract--This paper proposes an analytical model for ac-
curately predicting the impact of contention on cache miss
rates. The focus is multiprogrammed workloads running on
multithreaded manycore architectures. This work addresses a key
challenge facing earlier cache contention models as the number
of concurrent threads exceeds the associativity of shared caches.
The memory access characteristics of individual applications are
obtained in isolation by profiling their circular sequences and
two new measures of access locality are proposed. An evaluation
of this model in the context of a Niagara processor shows
that it achieves an average 8.7% error in miss rate predictions
which improves upon the best prior model by 48.1. This
paper also presents a novel Markov chain throughput model.
When combining the contention model with the Markov chain
model, throughput is estimated with an average error of 8.3%
compared to detailed simulation. Moreover, the combined model

  

Source: Aamodt, Tor - Department of Electrical and Computer Engineering, University of British Columbia

 

Collections: Engineering; Computer Technologies and Information Sciences