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Summary: CPPC: Correctable Parity Protected Cache
Mehrtash Manoochehri, Murali Annavaram and Michel Dubois
Ming Hsieh Department of Electrical Engineering
University of Southern California, Los Angeles
{mmanooch, annavara}@usc.edu, dubois@paris.usc.edu
ABSTRACT
Due to shrinking feature sizes processors are becoming more
vulnerable to soft errors. Write-back caches are particularly
vulnerable since they hold dirty data that do not exist in other
memory levels. While conventional error correcting codes can
protect write-back caches, it has been shown that they are
expensive in terms of area and power. This paper proposes a new
reliable write-back cache called Correctable Parity Protected
Cache (CPPC) which adds error correction capability to a parity-
protected cache. For this purpose, CPPC augments a write-back
parity-protected cache with two registers: the first register stores
the XOR of all data written to the cache and the second register
stores the XOR of all dirty data that are removed from the cache.
CPPC relies on parity to detect a fault and then on the two XOR
registers to correct faults. By a novel combination of byte shifting
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