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Microelectronics Journal 38 (2007) 706715 Using SAT-based techniques in power estimation

Summary: Microelectronics Journal 38 (2007) 706­715
Using SAT-based techniques in power estimation
Assim SagahyroonÃ, Fadi A. Aloul
Department of Computer Engineering, American University of Sharjah, UAE
Received 14 February 2006; received in revised form 8 April 2007; accepted 2 May 2007
Available online 27 June 2007
Recent algorithmic advances in Boolean satisfiability (SAT), along with highly efficient solver implementations, have enabled the
successful deployment of SAT technology in a wide range of applications domains, and particularly in electronic design automation
(EDA). SAT is increasingly being used as the underlying model for a number of applications in EDA. This paper describes how to
formulate two problems in power estimation of CMOS combinational circuits as SAT problems or 0­1 integer linear programming
(ILP). In these circuits, it was proven that maximizing dissipation is equivalent to maximizing gate output activity, appropriately
weighted to account for differing load capacitances. The first problem in this work deals with identifying an input vector pair that
maximizes the weighted circuit activity. In the second application we attempt to find an estimate for the maximum power-up current in
circuits where power cut-off or gating techniques are used to reduce leakage current. Both problems were successfully formulated as SAT
problems. SAT-Based and generic Integer Linear Programming (ILP) solvers are then used to find a solution. The experimental results
obtained on a large number of benchmark circuits provide promising evidence that the proposed complete approach is both viable and
useful and outperforms the random approach.
r 2007 Elsevier Ltd. All rights reserved.
Keywords: CMOS circuits; Power estimation; Optimization algorithms; Integer linear programming; Boolean satisfiability


Source: Aloul, Fadi - Department of Computer Engineering, American University of Sharjah


Collections: Engineering