Summary: Buffer Minimization in Pass Transistor Logic
Hai Zhou and Adnan Aziz
University of Texas at Austin
Austin, TX 78712
March 2, 1998
Since the technical limits of existing circuit families, such as static CMOS, alternative circuit
families are pursued for the development of chips that can operate at speeds significantly above
500 MHz. Among them, pass transistor logic (PTL) circuits offer great promise.
Since the delay in a passtransistor chain is quadratically proportional to its length, and a
signal may degenerate when pass through a transistor, buffers are necessary to guarantee the
performance and restore the signals in PTL. In this paper, we first analyze the effects of buffer
insertion on a circuit and give the sufficient and necessary condition for safe buffer insertion.
Then the buffer minimization problem is formulated, which asks for a minimum number of
buffers to make sure that no path has length longer than a given upper bound. Although NP
hard generally, when buffers are required on multiple fanouts, it can be solved linearly. We also
consider the case when buffers are inverters, where phase assignment need to be done with buffer
insertion. Experiments are done on MCNC logic synthesis and optimization benchmarks, and
compared with a levelbylevel insertion, a large number of buffers are reduced.