Summary: In IEEE Int'l Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, TX, March 2006.
Accelerating Architectural Exploration Using Canonical Instruction Segments
Rose F. Liu and Krste Asanovi´c
MIT Computer Science and Artificial Intelligence Laboratory
The Stata Center, 32 Vassar Street, Cambridge, MA 02139
rliu, krste¡ @csail.mit.edu
Abstract
Detailed microarchitectural simulators are not well suited
for exploring large design spaces due to their excessive sim-
ulation times. We introduce AXCIS, a framework for fast and
accurate design space exploration. AXCIS achieves fast sim-
ulation times by exploiting repetitions in program behavior to
reduce the number of instructions simulated. For each dynamic
instruction encountered during an initial full run of a bench-
mark, AXCIS builds an instruction segment, which concisely
represent performance-critical information. AXCIS then com-
presses the string of dynamic segments into a table of canon-
ical instruction segments (CIST) to give a compact represen-
tation of the entire benchmark trace. Given a precomputed
CIST and a target microarchitecture configuration, AXCIS can

Source: Asanoviæ, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

Collections: Computer Technologies and Information Sciences