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RAMP Blue: Implementation of a Manycore 1008 Processor FPGA System D. Burke, J. Wawrzynek, K. Asanovi, A. Krasnov, A. Schultz, G. Gibeling, P.-Y. Droz
 

Summary: RAMP Blue: Implementation of a Manycore 1008 Processor FPGA System
D. Burke, J. Wawrzynek, K. Asanovi, A. Krasnov, A. Schultz, G. Gibeling, P.-Y. Droz
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley
Berkeley, CA, USA
email:{drburke,johnw,krste,akrasnov,alschult,gdgib}@eecs.berkeley.edu, droz@ssl.berkeley.edu
Abstract
The RAMP project was undertaken based upon the
observation that future computer architectures were
likely to rely upon massive parallelism for
performance gains, whereas past gains largely
leveraged Moore's Law silicon improvements. A need
was perceived for an emulation platform to accelerate
architecture research and multicore/manycore
software engineering, specifically compiler and
parallel programming endeavors. The RAMP Blue
effort is a conventional direct RTL implementation of a
message-passing machine. The system consists of
768 1008 MicroBlaze cores in 6484 Virtex-II Pro 70
FPGAs on 1621 BEE2 boards, surpassing the

  

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Wawrzynek, John - Department of Electrical Engineering and Computer Sciences, University of California at Berkeley

 

Collections: Computer Technologies and Information Sciences