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Summary: Abstract
The trend towards deeper microprocessor pipelines
has made it advantageous or necessary to predict the
events that may happen in the stages ahead. A widely-used
example of this technique is latency speculation, where the
non-deterministic latency of some instructions, such as
loads, forces dependents to predict the number of clock
cycles these operations will take to complete execution. If
there is a misprediction, those dependents that issued
speculatively must be restarted or delayed appropriately
so that they can execute again with the correct inputs. This
process is called a scheduler replay. In the interest of
reducing the replay penalty, some recent designs, such as
the Pentium 4, have adopted selective replay mechanisms,
which reschedule only data-dependent instructions on a
latency misspeculation.
The deep pipelining trend has also forced designers to
reduce the circuit complexity of individual stages to main-
tain high clock speeds and to keep power dissipation man-
ageable. Tag elimination [4] is a technique used to reduce
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