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SiGe Digital Frequency Dividers with Reduced Residual Phase Noise
 

Summary: SiGe Digital Frequency Dividers with
Reduced Residual Phase Noise
Stephen Horst, Stan Phillips, Hossein Lavasani, Farrokh Ayazi, and John D. Cressler
School of Electrical and Computer Engineering
777 Atlantic Drive, N.W., Georgia Institute of Technology
Atlanta, Georgia 303320250 USA
E-mail: shorst@ece.gatech.edu
Abstract-- A new design methodology for achieving very low
residual phase noise in SiGe HBT digital frequency dividers is
presented. A modified CML D latch design is proposed that
enables the latch to draw more current, thereby reducing the
residual phase noise. The latch modification yields a 10 dB
phase noise improvement over a standard D latch topology, with
measurements at 10 GHz resulting in a phase noise floor of -
160 dBc/Hz. The circuit dissipates 350 mW of DC power, but
a standard phase noise figure-of-merit that accounts for phase
noise, DC power dissipation, and operating frequency, reveals
that this new design is among the best in its class.
I. INTRODUCTION
Frequency synthesis is a technique ubiquitous to modern

  

Source: Ayazi, Farrokh - School of Electrical and Computer Engineering, Georgia Institute of Technology

 

Collections: Engineering