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Static Scheduling of Instructions on Micronetbased Asynchronous Processors
 

Summary: Static Scheduling of Instructions on
Micronet­based Asynchronous Processors
D. K. Arvind and V. E. F. Rebello
Department of Computer Science, The University of Edinburgh
Edinburgh, EH9 3JZ, United Kingdom
E­mail: fdka, vefrg@dcs.ed.ac.uk
Abstract
This paper investigates issues which impinge on the
design of static instruction schedulers for micronet­
based asynchronous processor (MAP) architectures.
The micronet model exposes both temporal and spa­
tial concurrency within a processor. A list schedul­
ing algorithm is described which has been optimised
with MAP­specific heuristics. Their performance on
some program graphs are presented and conclusions
are drawn on the suitability of MAP as targets for ILP
compilers.
Keywords: Asynchronous Processor Architecture,
Instruction­level Parallelism (ILP), Micronets, Static
scheduling.

  

Source: Arvind, D. K. - School of Informatics, University of Edinburgh

 

Collections: Computer Technologies and Information Sciences