Home

About

Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network
FAQHELPSITE MAPCONTACT US


  Advanced Search  

 
A Case for FAME: FPGA Architecture Model Execution Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David Patterson
 

Summary: A Case for FAME: FPGA Architecture Model Execution
Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovi´c, David Patterson
The Parallel Computing Laboratory
CS Division, EECS Department, University of California, Berkeley
{xtan,waterman,hcook,slbird,krste,pattrsn}@eecs.berkeley.edu
ABSTRACT
Given the multicore microprocessor revolution, we argue
that the architecture research community needs a dramatic
increase in simulation capacity. We believe FPGA Archi-
tecture Model Execution (FAME) simulators can increase
the number of useful architecture research experiments per
day by two orders of magnitude over Software Architec-
ture Model Execution (SAME) simulators. To clear up
misconceptions about FPGA-based simulation methodolo-
gies, we propose a FAME taxonomy to distinguish the cost-
performance of variations on these ideas. We demonstrate
our simulation speedup claim with a case study wherein we
employ a prototype FAME simulator, RAMP Gold, to re-
search the interaction between hardware partitioning mech-
anisms and operating system scheduling policy. The study

  

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)

 

Collections: Computer Technologies and Information Sciences