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Simultaneous Multithreading: Maximizing OnChip Parallelism Dean M. Tullsen, Susan J. Eggers, and Henry M. Levy
 

Summary: Simultaneous Multithreading: Maximizing On­Chip Parallelism
Dean M. Tullsen, Susan J. Eggers, and Henry M. Levy
Department of Computer Science and Engineering
University of Washington
Seattle, WA 98195
Abstract
This paper examines simultaneous multithreading, a technique per­
mitting several independent threads to issue instructions to a su­
perscalar's multiple functional units in a single cycle. We present
several models of simultaneous multithreading and compare them
with alternative organizations: a wide superscalar, a fine­grain mul­
tithreaded processor, and single­chip, multiple­issue multiprocess­
ing architectures. Our results show that both (single­threaded) su­
perscalar and fine­grain multithreaded architectures are limited in
their ability to utilize the resources of a wide­issue processor. Si­
multaneous multithreading has the potential to achieve 4 times the
throughput of a superscalar, and double that of fine­grain multi­
threading. We evaluate several cache configurations made possible
by this type of organization and evaluate tradeoffs between them.
We also show that simultaneous multithreading is an attractive alter­

  

Source: Anderson, Richard - Department of Computer Science and Engineering, University of Washington at Seattle
Wang, Deli - Department of Electrical and Computer Engineering, University of California at San Diego

 

Collections: Computer Technologies and Information Sciences; Engineering; Materials Science