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Implementing the Scale Vector-Thread RONNY KRASHINSKY, CHRISTOPHER BATTEN, and KRSTE ASANOVI C
 

Summary: 41
Implementing the Scale Vector-Thread
Processor
RONNY KRASHINSKY, CHRISTOPHER BATTEN, and KRSTE ASANOVI ´C
Massachusetts Institute of Technology
The Scale vector-thread processor is a complexity-effective solution for embedded computing which
flexibly supports both vector and highly multithreaded processing. The 7.1-million transistor chip
has 16 decoupled execution clusters, vector load and store units, and a nonblocking 32KB cache.
An automated and iterative design and verification flow enabled a performance-, power-, and area-
efficient implementation with two person-years of development effort. Scale has a core area of
16.6 mm2 in 180 nm technology, and it consumes 400 mW­1.1 W while running at 260 MHz.
Categories and Subject Descriptors: C.5.3 [Computer System Implementation]: Microcom-
puters--Microprocessors; B.7.1 [Integrated Circuits]: Types and Design Styles--VLSI (very
large scale integration); C.1.2 [Processor Architectures]: Multiple Data Stream Architectures--
Single-instruction-stream, multiple-data-stream processors; multiple-instruction-stream, multiple-
data-stream processors; array and vector processors
General Terms: Design, Verification
Additional Key Words and Phrases: Vector processors, multithreaded processors, vector-thread
processors, iterative VLSI design flow, hybrid C++/Verilog simulation, procedural datapath pre-
placement

  

Source: Asanović, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, Networks and Mobile Systems Group

 

Collections: Computer Technologies and Information Sciences