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Design and Noise Analysis of 8Gb/s Capacitive Low Power and High Speed 4-PWAM Transceiver
 

Summary: Design and Noise Analysis of 8Gb/s Capacitive Low
Power and High Speed 4-PWAM Transceiver
Young Bok Kim and Yong-Bin Kim
Dept. of Electrical and Computer Engineering
Northeastern University
Boston, MA, USA
{youngbok, ybk }@ece.neu.edu
Abstract-- In this paper, capacitive 4-PWAM transmitter
architectures and circuits are proposed and its bit error rate is
estimated by developing noise model considering random jitter,
data dependent jitter, and PVT variations. A novel technique is
proposed to reduce power and to increase speed by using
capacitive driven low swing transceiver. To implement 4-PWAM
transmitter new phase controller and adaptive capacitance
network are designed. At receiver side, new architectures for
PWM and PAM demodulation are proposed and designed. The
proposed design saves 1.74~2.4x power and 4x higher data rate
than conventional designs.
I. INTRODUCTION
The environment of the communication channel and the

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering