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Summary: Analytical Surface Potential Model with Polysilicon Gate Depletion Effect for NMOS
E. Cumberbatch *
, H. Abebe **
, H. Morris***
and V. Tyree**
*
Claremont Graduate University, School of Mathematical Sciences, Claremont, California 91711, USA,
ellis.cumberbatch@cgu.edu
**
University of Southern California, Information Sciences Institute, MOSIS Service, 4676 Admiralty
Way, Marina del Rey, California 90292, USA, abebeh@mosis.org and tyree@mosis.org
***
Department of Mathematics, San Jose State University
San Jose, CA 95192, USA, morris@math.sjsu.edu
ABSTRACT
Different modeling approaches for the sub-100nm
MOSFET are discussed in [11] and the surface potential
description model is reported to be promising, [9, 11].
Surface potential changes impact gate capacitance and
current-voltage (I-V) characteristics of the MOS device at
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