Summary: An Embedded Low Power Reconfigurable Fabric For Finite State Machine
Zhenyu Liu', Tughrul Arslan" 2, Ahmet T. Erdogan" 2
School ofEngineering and Electronic, The University ofEdinburgh, King's Buildings,
Mayfield Road, Edinburgh EH9 3JL, UK.
Institute for System Level Integration, Livingston, EH54 7EG, UK
Abstract A novel generic reconfigurable Finite State The core is built with Verilog hardware description language
Machine (FSM) array architecture is presented in this paper. which can be synthesized with mainstream CAD tools. The
The architecture has been customized for reconfiguration architecture can implement generic FSMs with less area
targeting applications requiring large number of states with occupation and low power consumption when compared
the added advantage of low power consumption. Examples of with commercial FPGA devices.
up to 256 states have been targeted in this paper. Compared
with commercial FPGA devices, the new architecture provides The rest ofthe paper is organized as follows. In section 2
the following reductions: up to 89.3% in power consumption, we review the related work in the literature. Our architecture
up to 55.2% in area and around 8% in delay time. is described in details in section 3. Finally, the experimental
results and the conclusions are presented in sections 4 and 5.
II. RELATED WORK