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Summary: Token3D: Reducing Temperature in 3D die-stacked CMPs
through Cycle-level Power Control Mechanisms
Juan M. Cebrián1, Juan L. Aragón1
and Stefanos Kaxiras2
1
University of Murcia, Spain. {jcebrian, jlaragon}@ditec.um.es
2
University of Uppsala, Sweden. kaxiras@it.uu.se
Abstract. Nowadays, chip multiprocessors (CMPs) are the new standard design for
a wide range of microprocessors: mobile devices (in the near future almost every
smartphone will be governed by a CMP), desktop computers, laptop, servers, GPUs,
APUs, etc. This new way of increasing performance by exploiting parallelism has
two major drawbacks: off-chip bandwidth and communication latency between
cores. 3D die-stacked processors are a recent design trend aimed at overcoming
these drawbacks by stacking multiple device layers. However, the increase in
packing density also leads to an increase in power density, which translates into
thermal problems. Different proposals can be found in the literature to face these
thermal problems such as dynamic thermal management (DTM), dynamic voltage
and frequency scaling (DVFS), thread migration, etc. In this paper we propose the
use of microarchitectural power budget techniques to reduce peak temperature. In
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