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Optimizations Enabled by a Decoupled Front-End Architecture
 

Summary: Optimizations Enabled by a
Decoupled Front-End Architecture
Glenn Reinman, Brad Calder, Member, IEEE, and Todd Austin, Member, IEEE
Abstract–In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery
mechanism. Delivering the performance necessary to meet future processor execution targets requires that the performance of the
instruction delivery mechanism scale with the execution core. Attaining these targets is a challenging task due to I-cache misses,
branch mispredictions, and taken branches in the instruction stream. To counter these challenges, we present a fetch architecture that
decouples the branch predictor from the instruction fetch unit. A Fetch Target Queue (FTQ) is inserted between the branch predictor
and instruction cache. This allows the branch predictor to run far in advance of the address currently being fetched by the cache. The
decoupling enables a number of architecture optimizations, including multilevel branch predictor design, fetch-directed instruction
prefetching, and easier pipelining of the instruction cache. For the multilevel predictor, we show that it performs better than a single-
level predictor, even when ignoring the effects of cycle-timing issues. We also examine the performance of fetch-directed instruction
prefetching using a multilevel branch predictor and show that an average 19 percent speedup is achieved. In addition, we examine
pipelining the instruction cache to achieve a faster cycle time for the processor pipeline and show that pipelining provides an average
27 percent speedup over not pipelining the instruction cache for the programs examined.
Index Terms–Decoupled architectures, branch prediction, instruction prefetching, fetch architectures.
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1 INTRODUCTION
AT a high level, a modern high-performance processor is
composed of two processing engines: the front-end

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan

 

Collections: Engineering; Computer Technologies and Information Sciences