Summary: Heads and Tails: A Variable-Length Instruction Format
Supporting Parallel Fetch and Decode
Heidi Pan
MIT Laboratory for Computer Science
200 Technology Square
Cambridge, MA 02139
xoxo@lcs.mit.edu
Krste Asanovi´c
MIT Laboratory for Computer Science
200 Technology Square
Cambridge, MA 02139
krste@lcs.mit.edu
ABSTRACT
Existing variable-length instruction formats provide higher code
densities than fixed-length formats, but are ill-suited to pipelined
or parallel instruction fetch and decode. This paper presents a
new variable-length instruction format that supports parallel fetch
and decode of multiple instructions per cycle, allowing both high
code density and rapid execution for high-performance embedded
processors. In contrast to earlier schemes that store compressed

Source: Asanoviæ, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

Collections: Computer Technologies and Information Sciences