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Summary: An Efficient Single Copy Cache Coherence Protocol for
Multiprocessors with Multistage Interconnection Network.
Ragab Omran and Mokhtar Aboelaze
Department of Computer Science
York University, North York, Ontario,
CANADA, M3J 1P3
ABSTRACT
Multistage interconnection networks offer an efficient, scalable, and reasonable cost solu
tion for the problem of connecting processors to memory in a multiprocessor system. In
this paper, we present an efficient single copy cache coherence protocol for multiproces
sors with multistage interconnection network. Our protocol depends on incorporating the
cache memory into the switches of the multistage interconnection network. In our pro
posed protocol, data blocks move between the switches in order to minimize the memory
access time. We also develop a migration policy for data blocks not only to minimize the
average memory response time but also to minimize the overhead in locating a specific
memory block in case of a cache miss. We use two variations of our proposed protocol, the
first allows caches to be in the caching switches in the first stage of the interconnection
network only, while the second allows the switches to be in any switch in the intercon
nection network. We also use simulation to evaluate the performance of our protocol
and compare it with one of the existing cache coherence protocol for systems employing
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