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> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Figure 1. DICE cell [6]
 

Summary: > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1
Figure 1. DICE cell [6]
Abstract--The occurrence of multiple node upset is likely to
increase significantly in nanoscale CMOS due to reduced device
size and power supply voltage scaling. This paper presents a
comprehensive treatment (model, analysis and design) for
hardening storage elements (memories and latches) against a soft
error resulting in a multiple node upset at 32nm feature size in
CMOS. A novel 13T memory cell configuration is proposed,
analyzed, and simulated to show a better tolerance to the likely
multiple node upset. The proposed hardened memory cell utilizes a
Schmitt trigger design. s evidenced in past technical literature and
used in this paper, simulation of all node pairs by current sources
results in an assessment similar to 3D device tools; the simulation
results shows that the proposed 13T improves substantially over
DICE in the likely and realistic scenarios of very diffused or
limited charge sharing/collection. Moreover, the 13T cell achieves
a 33% reduction in write delay and only a 5% (9%) increase in
power consumption (layout area) compared to the DICE cell
(consisting of 12 transistors). The analysis is also extended to

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering