Home

About

Advanced Search

Browse by Discipline

Scientific Societies

E-print Alerts

Add E-prints

E-print Network
FAQHELPSITE MAPCONTACT US


  Advanced Search  

 
> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 A 13T CMOS Hardened Memory Cell for
 

Summary: > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1
A 13T CMOS Hardened Memory Cell for
Tolerance to a Single Event with Multiple Node
Upsets
Sheng Lin, Student Member, IEEE, Yong-Bin Kim, Senior Member, IEEE, and Fabrizio Lombardi,
Fellow, IEEE
Abstract--The occurrence of a single event causing multiple
node upsets is likely to increase significantly in nanoscale CMOS
due to reduced device size and power supply voltage scaling. This
paper presents a comprehensive treatment (model, analysis and
design) for hardening a memory cell against a soft error resulting
in multiple node upsets at 32nm feature size in CMOS. A novel
13T memory cell configuration is proposed, analyzed, and
simulated to show a better tolerance to the likely multiple node
upsets, i.e. a transient or soft fault affecting two nodes in a cell.
The proposed hardened memory cell utilizes a Schmitt trigger
design. As evidenced in past technical literature and used in this
paper, simulation of all node pairs by current sources results in an
assessment similar to 3D device tools; the simulation results shows
that the proposed 13T improves substantially over DICE in the

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering