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JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO.4, DECEMBER, 2007 161 Manuscript received Nov. 3, 2007; revised Nov. 30, 2007.
 

Summary: JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO.4, DECEMBER, 2007 161
Manuscript received Nov. 3, 2007; revised Nov. 30, 2007.
* Department of Electrical and Computer Engineering,
Northeastern University, Boston, MA, USA
E-mail : kkkim@ece.neu.edu, ybk@ece.neu.edu
** NextChip Corp. Seoul, Korea
E-mail : yjlee@nextchip.com
Phase-Locked Loop with Leakage and Power/Ground
Noise Compensation in 32nm Technology
Kyung Ki Kim*, Yong-Bin Kim*, and Young Jun Lee**
Abstract--This paper presents two novel compen-
sation circuits for leakage current and power supply
noise (PSN) in phase locked loop (PLL) using a
nanometer CMOS technology. The leakage compen-
sation circuit reduces the leakage current of the charge
pump circuit and the PSN compensation circuit
decreases the effect of power supply variation on the
output frequency of VCO. The PLL design is based
on a 32nm predictive CMOS technology and uses a
0.9 V power supply voltage. The simulation results

  

Source: Ayers, Joseph - Marine Science Center & Department of Biology, Northeastern University

 

Collections: Engineering