Summary: 1
LOGIC DESIGN VALIDATION VIA SIMULATION AND AUTOMATIC
TEST PATTERN GENERATION1
Hussain Al-Asaad*
and John P. Hayes**
*
Computer Engineering Research Laboratory
Department of Electrical and Computer Engineering
University of California
One Shields Avenue, Davis, CA 95616-5294
**Advanced Computer Architecture Laboratory
Department of Electrical Engineering and Computer Science
University of Michigan
1301 Beal Avenue, Ann Arbor, MI 48109­2122
Submitted August 1999, Revised April 2000
ABSTRACT
We investigate an automated design validation scheme for gate-level combinational and
sequential circuits that borrows methods from simulation and test generation for physical faults,
and verifies a circuit with respect to a modeled set of design errors. The error models used in prior
research are examined and reduced to five types: gate substitution errors (GSEs), gate count

Source: Al-Asaad, Hussain - Department of Electrical and Computer Engineering, University of California, Davis

Collections: Computer Technologies and Information Sciences