A New Method for Power Estimation and
Optimization of Combinational Circuits
Ahmed Sammy Aldeen
Intel Corporation, Folsom, CA.
University of California, Davis, CA.
Abstract -- One of the challenges of low power
methodologies for digital systems is saving power
consumption in these systems without compromising
performance. In this paper we propose a new method for
estimating dynamic power consumption in combinational
circuits. The method enables us to optimize the power
consumption of typical combinational circuits.
Index Terms -- Power estimation, power optimization,
low-power design, combinational circuits.
To address the areas of power estimation and
optimization, we would revisit the basic CMOS power
consumption equations. There are three major sources