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Enabling Parallelization via a Reconfigurable Chip Multiprocessor
 

Summary: Enabling Parallelization via
a Reconfigurable Chip Multiprocessor
Matthew A. Watkins
Cornell University
Computer Systems Laboratory
David H. Albonesi
Cornell University
Computer Systems Laboratory
ABSTRACT
While reconfigurable computing has traditionally involved attach-
ing a reconfigurable fabric to a single processor core, the prospect
of large-scale CMPs calls for a reevaluation of reconfigurable com-
puting from the perspective of multicore architectures. We present
ReMAPP, a reconfigurable architecture geared towards application
acceleration and parallelization. In ReMAPP, parallel threads share
a common reconfigurable fabric which can be configured for indi-
vidual thread computation or fine-grained communication with in-
tegrated computation. The architecture supports both fine-grained
barrier synchronization and fine-grained point-to-point communi-
cation for pipeline parallelization.

  

Source: Albonesi, David H. - Computer Systems Laboratory, Cornell University

 

Collections: Computer Technologies and Information Sciences