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Re-Usable Low Power DSP IP embedded in an ARM based SoC Architecture

Summary: Re-Usable Low Power DSP IP embedded in an
ARM based SoC Architecture
H. H. Hellmich, A. T. Erdogan, and T. Arslan*
The integration of different re-usable IPs (Intellectual Properties) to design SoC (System-on-Chip) de-
vices is widely accepted as the key to achieving higher productivity to meet shorter time-to-market de-
mands. Nevertheless, productivity improvements suffer because the importance of interface definitions
and consequently the integration of IPs for the targeted SoC architecture is often treated as a secondary
issue. This paper describes a scheme for the integration of a low power DSP IP embedded in an ARM
based SoC architecture which is characterised by having two interfaces intended for two different types
of on-chip bus configurations. A DSP IP has been implemented using this scheme. The power consump-
tion of the actual FIR filtering algorithm realised within the DSP IP has been compared to a conventio-
nal implementation using an Alcatel 0.35 Ám CMOS technology.
1. Introduction
The growing gap between the silicon gate capacity and the engineering productivity has lead to the ad-
vance of complex SoC designs and the need for new forms of design reuse and design methodologies
[Bric99]. In order to overcome this gap, design reuse is migrating from source reuse to integration-driven
reuse and design methodologies are changing from TDD (Timing-Driven Design) to PBD (Platform-
Based Design) [Chang99]. However, PBD gains its productivity by minimising the amount of custom
interface design and focuses around a standardised bus architecture.


Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh


Collections: Engineering