Summary: MIT CSAIL Technical Report (MIT-LCS-TR-957), July 2004 1
Dynamically Resizable Static CMOS Logic for Fine-Grain Leakage Reduction
Seongmoo Heo and Krste Asanovi´c
MIT Computer Science and Artificial Intelligence Laboratory
32 Vassar Street, Cambridge, MA 02139
heomoo,krste@csail.mit.edu
Abstract
Digital circuits often have a critical path that runs
through a small subset of the component subblocks, but
where the path changes dynamically during operation. Dy-
namically resizable static CMOS (DRCMOS) logic is pro-
posed as a fine-grain leakage reduction technique that dy-
namically downsizes transistors in inactive subblocks while
maintaining speed in subblocks along the current critical
path. A 64-entry register free list and a 64-entry pick-two
arbiter are used to evaluate DRCMOS. DRCMOS is shown
to give a 50% reduction in total power for equal delay in a
70nm technology.
1 Introduction
Power has become one of the primary design constraints

Source: Asanovic, Krste - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Massachusetts Institute of Technology (MIT), Computer Science and Artificial Intelligence Laboratory, SCALE Group

Collections: Computer Technologies and Information Sciences