Summary: Scalar Operand Networks:
On-Chip Interconnect for ILP in Partitioned Architectures
Michael Bedford Taylor, Walter Lee, Saman Amarasinghe, Anant Agarwal
MIT Laboratory for Computer Science
ABSTRACT
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Source: Amarasinghe, Saman - Computer Science and Artificial Intelligence Laboratory & Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (MIT)
Gupta, Rajiv - Department of Computer Science and Engineering, University of California at Riverside
Massachusetts Institute of Technology (MIT), Department of Electrical Engineering and Computer Science, RAW Project
Wang, Deli - Department of Electrical and Computer Engineering, University of California at San Diego

Collections: Computer Technologies and Information Sciences; Engineering; Materials Science