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A Band-Reject Nested-PLL Phase-Noise Reduction Scheme for Clock-Cleaners

Summary: A Band-Reject Nested-PLL Phase-Noise Reduction
Scheme for Clock-Cleaners
Mauricio Pardo1,2
, Farrokh Ayazi1
Georgia Institute of Technology, Atlanta, Georgia, USA
Fundación Universidad del Norte, Barranquilla, Colombia
Email: mpardo@gatech.edu
Abstract--This paper proposes a clock-conditioner architecture
that minimizes the incidence of the input signal phase-noise
(PN) in phase-locked-loop (PLL)-based cleaners by modifying
the corresponding transfer function from band-pass to
band-reject. Although the proposed configuration uses two
PLLs, just one cut-off frequency exists eliminating the need for
ultra narrow-band loops. Relaxed bandwidth requirements
translate to smaller capacitor values in the loop filters which
considerably reduce the overall footprint of the architecture. A
100 MHz clock-cleaner is demonstrated using ICs fabricated in
a 0.5 µm 2P3M CMOS process. Experimental results show a


Source: Ayazi, Farrokh - School of Electrical and Computer Engineering, Georgia Institute of Technology


Collections: Engineering