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Summary: ABSTRACT
In this paper, we survey various designs of low-power
full-adder cells from conventional CMOS to really inven-
tive XOR-based designs. We further describe simulation
experiments that compare the surveyed full-adder cells.
The experiments simulate all combinations of input transi-
tions and consequently determine the delay and power
consumption for the various full-adder cells. Moreover, the
simulation results highlight the weaknesses and the
strengths of the various full-adder cell designs.
Keywords: Full-adder cell design, low-power cir-
cuits, power and delay estimation, VLSI implementa-
tions.
1 INTRODUCTION
Low power circuit design has been a challenge for
a long time and it is now one of the most important
goals of today's CMOS designs. Signal processing is
one of the most power hungry applications. Adders
are the main building blocks for signal processing
applications. Saving power in adders would reduce
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