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Summary: IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. , NO. , JUNE 2008 1
A Novel Statistical Timing and Leakage Power
Characterization of Partially-Depleted
Silicon-On-Insulator (SOI) Gates
Kyung Ki Kim, Yong-Bin Kim, Senior Member, IEEE and Fabrizio Lombardi Senior Member, IEEE
Abstract--This paper presents a novel statistical characteriza-
tion for accurate timing and a new probabilistic based analysis for
estimating the leakage power in Partially-Depleted Silicon-On-
Insulator (PD-SOI) circuits in BSIMSOI3.2 100nm technology.
This paper shows that the accuracy of modeling the leakage
current in PD-SOI CMOS circuits is improved by considering
the interactions between the subthreshold leakage and the gate
tunneling leakage, the stacking effect, the history effect, and the
fanout effect along with a new input-independent method for
estimating the leakage power based on a probabilistic approach.
The proposed timing and leakage power estimate algorithms are
implemented in Matlab, Hspice, and C. The proposed method-
ology is applied to ISCAS85 benchmarks, and the results show
that the error is within 5% compared with random simulation
results.
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