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IEE Electronics Letters, vol. 32, no. 21, pp. 195960, 10 th October 1996. A LOW POWER MULTIPLICATION SCHEME FOR FIR FILTER IMPLEMENTATION ON
 

Summary: IEE Electronics Letters, vol. 32, no. 21, pp. 1959­60, 10 th October 1996.
1
A LOW POWER MULTIPLICATION SCHEME FOR FIR FILTER IMPLEMENTATION ON
SINGLE MULTIPLIER CMOS DSP PROCESSORS
A.T. Erdogan and T. Arslan
The University of Wales Cardiff,
Cardiff School of Engineering,
Cardiff CF2 1XH,
United Kingdom
Indexing terms: Low power, VLSI, Digital Signal Processing
Abstract: A new multiplication scheme is proposed targeting single multiplier CMOS based
DSP processors, for the implementation of low­power digital FIR filters through the
reduction of switching activity within the multiplier section of the filter. The scheme operates
in conjunction with a transpose direct form FIR filter structure and a modified DSP processor
architecture which is open to exploitation by algorithms for achieving significant reduction in
power by ordering the filter coefficients. This reduction is demonstrated using two basic
examples, with different wordlengths and filter orders, achieving up to 63% reduction in
switching activity.
Introduction: Power dissipation is becoming a limiting factor in the realisation of VLSI systems.
Because of their relatively greater complexity power dissipation in Digital Signal Processing (DSP)

  

Source: Arslan, Tughrul - School of Engineering and Electronics, University of Edinburgh

 

Collections: Engineering