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b-sing Speculative Retirement and Larger Instruction Lvindows to Narrow the Performance Gap between Memory Consistency Models *
 

Summary: b-sing Speculative Retirement and Larger Instruction Lvindows to Narrow the
Performance Gap between Memory Consistency Models *
Parthasarathy Ranganathan, Vijay S. Pai, and Sarita V. Adve
Department of Electrical and Computer Engineering
Rice University
Houston, Texas 77005
{parthas Ivi jaypai Isarita}~rice. edu
Abstract
This paper studies techniques to improue the performance
of memory consistency models for shared-memory multi-
processors with ILP processors. The first part of this pa-
per extends earlier work by studying the impact of current
hardware optimization to memory consistency implementa-
tions, hardware-controlled non-binding prefetching and spec-
ulative load execution, on the performance of the processor
consistency (PC) memory model. We find that the opti-
mized implementation of PC performs significant tly better
than the best implementation of sequential consistency (SC)
in some cases because PC relaxes the store-to-load ordering
constraint of SC. Nevertheless, release consistency (RC) pro-

  

Source: Adve, Sarita - Department of Computer Science, University of Illinois at Urbana-Champaign

 

Collections: Computer Technologies and Information Sciences