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VLSI Implementation of Rake Receiver for IS-95 CDMA Testbed using Oliver Leung Chi-ying Tsui Roger S. Cheng
 

Summary: VLSI Implementation of Rake Receiver for IS-95 CDMA Testbed using
FPGA
Oliver Leung Chi-ying Tsui Roger S. Cheng
Department of Electrical and Electronic Engineering
Hong Kong University of Science and Technology
e-mail: cpegfa@ee.ust.hk e-mail: eetsui@ee.ust.hk e-mail: eecheng@ee.ust.hk
Abstract| Inthis w ork, an implementation of a time-
multiplexed downlink Rake receiv er complied with the IS-
95 CDMA standard is presented. A low pow er architecture
of the Rake receiver is implemented. A structure which
provides the o set changing for the pseudo-random se-
quence (PN sequence) used for despreading of the CDMA
signals is discussed. Arc hitecture for the e cient time mul-
tiplexing of the Rake ngers is also presented. The de-
sign was implemented using Xilinx FPGA. It was tested to
be functionally correct and the performance was complied
with IS-95.
I. Introduction
Code-division Multiple Access (CDMA) has becomev ery pop-
ular in wireless communication systems. IS-95 CDMA Testbed is

  

Source: Arslan, Hüseyin - Department of Electrical Engineering, University of South Florida

 

Collections: Engineering