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Alleviating Thermal Constraints While Maintaining Performance Via Silicon-Based On-Chip Optical Interconnects
 

Summary: Alleviating Thermal Constraints While Maintaining Performance
Via Silicon-Based On-Chip Optical Interconnects
Nicholas Nelson, Gregory Briggs, Mikhail Haurylau, Guoqing Chen, Hui Chen
David H. Albonesi
, Eby G. Friedman, and Philippe M. Fauchet
Department of Electrical and Computer Engineering
University of Rochester, Rochester, New York 14627

Computer Systems Laboratory
Cornell University, Ithaca, New York 14853
Abstract
The relentless pursuit of Moore's Law by the
semiconductor industry has yielded significant in-
creases in performance, but at the cost of greater
power dissipation. As CMOS technology continues
to scale, increasing power densities, or "hot spots,"
particularly in dense logic structures, may limit fre-
quencies below projected targets in order to avoid
circuit malfunction. A solution to this problem
is to separate the hot spots by interleaving these

  

Source: Albonesi, David H. - Computer Systems Laboratory, Cornell University
Friedman, Eby G. - Department of Electrical and Computer Engineering, University of Rochester

 

Collections: Computer Technologies and Information Sciences; Engineering