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Summary: Soft Error Benchmarking of L2 Caches with PARMA
Jinho Suh, Mehrtash Manoochehri, Murali Annavaram and Michel Dubois
Ming Hsieh Department of Electrical Engineering
University of Southern California, Los Angeles
{jinhosuh, mmanooch, annavara}@usc.edu, dubois@paris.usc.edu
ABSTRACT
The amount of charge stored in an SRAM cell shrinks rapidly
with each technology generation thus increasingly exposing
caches to soft errors. Benchmarking the FIT rate of caches due to
soft errors is critical to evaluate the relative merits of a plethora of
protection schemes that are being proposed to protect against soft
errors. The benchmarking of cache reliability introduces a unique
challenge as compared to internal processor storage structures,
such as the load/store queue. In the case of internal processor
structures the time a data bit resides in the structure is so short that
it is generally safe to assume that no more than one soft error
strike can occur. Thus the reliability of such structures is
overwhelmingly dominated by single bit errors. By contrast, a
memory block may reside for millions of cycles in a last level
cache. In this case it is important to consider the impact of the
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