Summary: Model Checking the IBM Gigahertz Processor:
An Abstraction Algorithm for High­Performance
Netlists
Jason Baumgartner 1 , Tamir Heyman 2 , Vigyan Singhal 3 , and Adnan Aziz 4
1 IBM Corporation, Austin, Texas 78758, USA,
jasonb@austin.ibm.com
2 IBM Haifa Research Laboratory, Haifa, Israel,
tamirh@vnet.ibm.com
3 Cadence Berkeley Labs, Berkeley, California 94704, USA,
vigyan@cadence.com
4 The University of Texas at Austin, Austin, Texas 78712, USA,
adnan@ece.utexas.edu
Abstract. A common technique in high­performance hardware design
is to intersperse combinatorial logic freely between level­sensitive latch
layers (wherein one layer is transparent during the ``high'' clock phase,
and the next during the ``low''). Such logic poses a challenge to verifica­
tion -- unless the two­phase netlist N may be abstracted to a full­cycle
model N 0 (wherein each memory element may sample every cycle), model
checking of N requires at least twice as many state variables as would be
necessary to obtain equivalent coverage for N 0 . We present an algorithm

Source: Aziz, Adnan - Department of Electrical and Computer Engineering, University of Texas at Austin

Collections: Computer Technologies and Information Sciences