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High-Bandwidth Address Translation for Multiple-Issue Processors
 

Summary: High-Bandwidth Address Translation
for Multiple-Issue Processors
Todd M. Austin Gurindar S. Sohi
Computer Sciences Department
University of Wisconsin-Madison
1210 W. Dayton Street
Madison, WI 53706
faustin,sohig@cs.wisc.edu
Abstract
In an effort to push the envelope of system performance, mi-
croprocessor designs are continually exploiting higher levels of
instruction-level parallelism, resulting in increasing bandwidth de-
mands on the address translation mechanism. Most current micro-
processor designs meet this demand with a multi-ported TLB. While
this design provides an excellent hit rate at each port, its access la-
tency and area grow very quickly as the number of ports is increased.
As bandwidth demands continue to increase, multi-ported designs
will soon impact memory access latency.
We present four high-bandwidth address translation mechanisms
with latency and area characteristics that scale better than a multi-

  

Source: Austin, Todd M. - Department of Electrical Engineering and Computer Science, University of Michigan

 

Collections: Engineering; Computer Technologies and Information Sciences