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Summary: A Multizone Pipelined Cache for IP Routing
Soraya Kasnavi, Paul Berube, Vincent C. Gaudet, and Jos´e Nelson Amaral
Dept. of Electrical and Computer Engineering, University of Alberta
Edmonton, Alberta, T6G 2V4, Canada
kasnavi,vgaudet@ece.ualberta.ca
berube, amaral@cs.ualberta.ca
Abstract. Caching recently referenced IP addresses and their forwarding in-
formation is an effective strategy to increase routing lookup speed. This paper
proposes a multizone non-blocking pipelined cache for IP routing lookup that
achieves lower miss rates compared to previously reported IP caches. The two-
stage pipeline design provides a half-prefix half-full address cache and reduces
the cache power consumption. By adopting a very small non-blocking buffer, the
cache reduces the effective miss penalty. This cache design takes advantage of
storing prefixes but requires smaller table expansions (up to 50% less) compared
with prefix caches. Simulation results on real traffic display lower cache miss rate
and up to 30% reduction in power consumption.
Key words: IP lookup, IP Caching, Content Addressable Memory (CAM).
1 Introduction
The sustained increase in Internet traffic over the last decade has necessitated faster and
faster backbone networks and a corresponding increase in network processor through-
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