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FPGA ARCHITECTURE FOR REAL-TIME VIDEO NOISE ESTIMATION Francois-Xavier Lapalme, Aishy Amer, and Chunyan Wang
 

Summary: FPGA ARCHITECTURE FOR REAL-TIME VIDEO NOISE ESTIMATION
Franc¸ois-Xavier Lapalme, Aishy Amer, and Chunyan Wang
Concordia University , Electrical and Computer Engineering
Montr´eal, Qu´ebec, Canada
email: {f lapalm,amer,chunyan}@ece.concordia.ca
ABSTRACT
This paper proposes a hardware architecture of a video noise estima-
tion algorithm capable of real-time processing. The objectives con-
sist of adapting a computationally demanding noise estimation algo-
rithm to a synthesizable VHDL implementation and achieving real-
time performance. This Structure-oriented noise estimation method
considers image structure to find intensity-homogeneous blocks. Sub-
sequently, these blocks are included in the averaging process to es-
timate the noise variance. Generating worst-case estimation error of
3 dB, this spatial noise reduction method is reliable for highly noisy
and textured images. The proposed architecture provides a satisfac-
tory compromise between area and processing speed. Furthermore,
parameterization of the architecture allows additional flexibility with
the scaling of mask sizes that can operate on 3x3 or 5x5 blocks of
pixels. The proposed design is targeted to an FPGA device and esti-

  

Source: Amer, Aishy - Department of Electrical and Computer Engineering, Concordia University

 

Collections: Engineering