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Global Multi-Threaded Instruction Scheduling Guilherme Ottoni David I. August

Summary: Global Multi-Threaded Instruction Scheduling
Guilherme Ottoni David I. August
Department of Computer Science
Princeton University
{ottoni, august}@princeton.edu
Recently, the microprocessor industry has moved toward
chip multiprocessor (CMP) designs as a means of utiliz-
ing the increasing transistor counts in the face of physi-
cal and micro-architectural limitations. Despite this move,
CMPs do not directly improve the performance of single-
threaded codes, a characteristic of most applications. In or-
der to support parallelization of general-purpose applica-
tions, computer architects have proposed CMPs with light-
weight scalar communication mechanisms [21, 23, 29]. De-
spite such support, most existing compiler multi-threading
techniques have generally demonstrated little effective-
ness in extracting parallelism from non-scientific applica-
tions [14, 15, 22]. The main reason for this is that such
techniques are mostly restricted to extracting parallelism


Source: August, David - Department of Computer Science, Princeton University


Collections: Computer Technologies and Information Sciences