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Simultaneous PTL Buffer Insertion and Sizing for Minimizing Elmore Delay
 

Summary: Simultaneous PTL Buffer Insertion and Sizing for
Minimizing Elmore Delay
I­Min Liu y Tai­Hung Liu y Hai Zhou z Adnan Aziz y
y Electrical and Computer Engineering z Computer Sciences
The University of Texas The University of Texas
Austin TX Austin TX
Abstract
For many digital designs, implementation in pass
transistor logic (PTL) has been shown to be superior
in terms of area, timing, and power characteristics
to static CMOS. One problem with PTL circuits is
that the delay through serially connected transistors
is quadratic in the number of stages. The objective
of this work is to develop an automatic PTL buffer
insertion and sizing procedure for minimizing Elmore
delay.
1 Introduction
For many complex logic functions, implementation in
pass­transistor logic has been shown to be superior to
static CMOS [1, 2, 3, 4]. Advantages of PTL include

  

Source: Aziz, Adnan - Department of Electrical and Computer Engineering, University of Texas at Austin
Zhou, Hai - Department of Electrical and Computer Engineering, Northwestern University

 

Collections: Computer Technologies and Information Sciences