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Summary: Fault-tolerant cache coherence protocols for
CMPs: evaluation and trade-offs
Ricardo Fern´andez-Pascual1
, Jos´e M. Garc´ia1
, Manuel E. Acacio1
and Jos´e Duato2
1
Departamento de Ingenier´ia y Tecnolog´ia de Computadores
Universidad de Murcia, 30100 Murcia (Spain)
{rfernandez,jmgarcia,meacacio}@ditec.um.es
2
Dpto. de Inform´atica de Sistemas y Computadores
Universidad Polit´ecnica de Valencia, 46022 Valencia (Spain)
jduato@disca.upv.es
Abstract. One way of dealing with transient faults that will affect the
interconnection network of future large-scale Chip Multiprocessor (CMP)
systems is by extending the cache coherence protocol. Fault tolerance at
the level of the cache coherence protocol has been proven to achieve very
low performance overhead in absence of faults while being able to support
very high fault rates. In this work, we compare two already proposed
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